Phase lock loops (PLL) typically include a phase frequency detector (PFD) that provides control signals indicative of a phase difference between a reference clock and an oscillation signal or a VCO clock of a voltage controlled oscillator (VCO). A charge pump provides a voltage signal to the VCO in response to the control signals. The VCO provides the oscillation signal responsive to the voltage signal.
As the frequency of the reference clock is increased, the performance requirements of the phase lock loop becomes more stringent. A high performance PLL has low clock jitter at its operation frequency. The PLL jitter is caused by two major factors. First, the supply noise can abruptly change the frequency of the VCO and result in PLL clock output jitter. This type of jitter can be reduced by increasing the noise immunity of the VCO circuitry. The second major factor is the precision of the phase frequency detector. A low precision of phase frequency detector typically has a large minimum detectable phase difference (or “dead zone”), which increases the jitter. The jitter caused by the low precision phase frequency detector can be reduced by increasing the precision of the phase frequency detector. A phase frequency detector including a conventional static logic gate structure has a speed limitation due to the propagation delay through multiple logic gate stages. This speed limitation increases the dead zone in the operation of the phase frequency detector at high frequency, and hence increases the jitter.
It is desirable to have a PLL that operates at higher frequencies with less jitter.